ARM hair CoreLink system IP phone CPU to the Great Leap Forward

Recently, ARM announced the launch of two new enhanced version Corelink system IP, one is CoreLink CCI-550 interconnect bus for big.LITTLE multi-core architecture, complete consistency GPU, and lower latency, higher throughput, another It is CoreLink DMC-500 memory controller, higher bandwidth, lower latency. This is the future of ARM chips foundation heterogeneous systems.

According to ARM, said, CCI-550 and in February this year along with Cortex-A72 CPU core of the birth of CCI-500, are Qualcomm, MediaTek widespread use of replacement CCI-400, the biggest change is the addition of sniffer filter (snoop filter), instead of the first generation of the size of the core architecture in the broadcast design, while all the cores, caches to communicate with, and therefore lower latency, greater scalability, and lower power consumption (saving up to hundreds of milliwatts), higher performance . SoC designers can configure the memory channel number, size tracker, sniffer filter capacity and six processor group.

CCI-400 can support two CPU cluster (cluster), CCI-500 doubled to four, the new CCI-550 can be interconnected 则 only six CPU cluster, also supports the complete consistency of CPU / GPU hybrid interconnection, and increase the read data buffer, sniffing data bandwidth doubled system bandwidth of more than 50GB / s. CCI-550 also supports up to six memory channels (32-48-bit physical addressing), three main interface, six ACE main port. The technology is applicable to 4K imaging, and automotive and network application mobile phones and digital television, the entire processor core 24 can be done.

CoreLink DMC-500 is an upgraded version of the DMC-400 can support LPDDR4 / 3 with the highest LPDDR4-4267 storage specifications. In the overall design level, CoreLink CCI-550 and CoreLink DMC-500 can work together to achieve more than 50GB / s peak bandwidth of the system memory can be used in tablets and smartphones 4K video.

The Linley Group senior analyst Mike Demle said: "If you want to provide customers with advanced features such as 4K video recording and playback, 120fps camera, 4K HD display, etc., then you surely need to be heterogeneous CPU, GPU and accelerator in the same cache system synchronization, and also must be strict control of power. "

CoreLink CCI-550, CoreLink DMC-500 related products have been handed over to the main partners, is expected to come out during the second half of 2016, under the new process frequency can be more than 1GHz.